Таблица 4.1
ПРОГРАММИРОВАНИЕ
Uпрогр=12 В tпрогр=1 mS
Uпрогр=13 В tпрогр=1 mS
Uпрогр=14В tпрогр=1 mS
Uпрогр=15 tпрогр=1 mS
Uпрогр=16В tпрогр=1 mS
Uпор,В Iст=0.1 мкА, Uс=Uз, Uи=0,Uп=0В
Экпери-мент
Моделиро-вание
0,10
0,21
0,60
0,49
1,30
1,41
1,90
2,08
2,60
2,73
0,02
0,032
0,51
1,25
1,34
2,03
2,71
0,12
0,23
0,71
1,35
2,05
2,70
0,00
0,05
0,25
0,35
0,75
0,80
1,50
1,63
2,00
2,11
0,031
0,24
0,33
1,15
1,28
1,60
1,71
2,15
2,23
0,04
0,30
0,41
1,10
1,22
2,20
2,30
0,31
0,95
1,00
1,72
2,29
2,90
3,00
1,07
2,31
2,80
2,93
1,05
1,16
2,40
2,52
3,01
СТИРАНИЕ
Uстир=12 В tстир=1 mS
Uстир=13 В tстир=1 mS
Uстир=14В tстир=1 mS
Uстир=15 tстир=1 mS
Uстир=16В tстир=1 mS
Uпор,В Iст=0.1 мкА, Uс=2В, Uи=0,Uп=0В
Модели-рование
+0,85
+0,9
+1,24
+1,3
-1,50
-1,4
-2,14
-2,03
-3,50
-3,41
+0,95
+1,0
+0,32
+40,41
-1,54
-1,49
-2,40
-2,34
-3,42
-3,31
+1
+1,1
+0,4
+0,49
-1,40
-1,3
-2,70
-2,61
-4,00
-3,91
+1,22
+0,51
-1,37
-1,25
-2,32
-2,25
-3,30
-3,19
+1,25
+0,53
-1,28
-1,19
-2,30
-2,21
-3,34
-3,25
СПИСОК ИСПОЛЬЗУЕМОЙ ЛИТЕРАТУРЫ
1. Статьи из IEEE JOURNAL OF SOLID-STATE CIRCUITS:
2. “A 16kbit EEPROM Using n-Channel Si-Gate MOS Technology” June1980, number 3, vol. sc-15; TAYAAKI HAGIWARA, YUJI YANSUDA, RYUJI KONDO, SHIN-ICHI MINAMI, TOSHIRO AOTO, and YOKICHI ITOH.
3. “ A 16kbit EEPROM Employing New Array Architecture and Designed-In Reliability Features” October1982, number 5, vol. sc-17; GIORA YARON, S. JAYASIMHA PRASAD, MARK S. EBEL, and BRUCE M. K. LEONG.
4. “ A 128kbit Flash EEPROM Using Double-Polysilicon Technology” October1987, number 5, vol. sc-22; GHEORGHE SAMASHISA, CHIEN-SHENG SU, YU SHENG KAO, GEORGE SMARANDOIU, CHENG-YUAN MICHAEL WANG, TINGWONG, CHENMING HU.
5. “A 50-ns CMOS 256K EEPROM ” October 1988 number 5 vol.23; TAH-KANG J.TING, THOMAS CHANG,TIEN LIN,CHING S. JENQ,KENNETH L. C. NAIFF.
6. “An 80ns 32K EEPROM Using the FETMOS Cell”October1982 number 5, vol. sc-17 ;CLINTON KUO,JOHN R. YEARGAIN,WILLIAM J. DOWNEY,KERRY A.ILGENSTEIN,JEFFREY R.JORVIG,STEPHEN L.SMITH,ALAN R. BORMANN.
7. “An Enhanced 16K EEPROM” October 1982 number 5 vol.sc-17; LUBIN GEE, PEARL CHENG, YOGENDRA BOBRA,RUSTAM MENTA.
8. “A 5-V-ONLY one-Transistor 256K EEPRON with Rage-Mode Erase” August 1989 number 4 vol.24; TAKESHI NAKAYAMA, YOSHIKAZU MIYAWAKI, KAZUO KOBAYASHI, YASUSHI TERADA, HIDEAKI ARIMA,TAKAYUKI, MATSUKAWA,TSUTOMU YOSHIHARA.
9. “An Experimental 4-Mbit CMOS EEPROM with a NAND-structured Cell” October 1989 number 5 vol.24;MASAKI MOMODOMI,YASUO ITOH,RIICHIRO SHIROTA,YOSHIHISA IWATA,RYOZO MAKAYAMA,RYOUHEI KIRISAWA,TOMOHARU TANAKA,SEIICHI ARITOME,TETSUO ENDOH,KAZUNORI OHUCHI,FUJIO MASUOKA.
10. “120-ns 128K /8bit/64K/16bit CMOS EEPROM’S” October 1989 number 5 vol.24;YASUSHI TERADA, KAZUO KOBAYASHI,TAKESHI NAKAYAMA,MASANORI HAYASAIKOSHI,YOSHIKAZU MIYAWAKI,NATSUO AJIKA, HIDEAKI ARIMA,TAKAYUKI MATSUKAWA,TSUTOMU YOSHIHARA.
11. “Yield and Reliability of MNOS EEPROM Products” December 1989 number 6 vol.24 ; YOSHIAKI KAMIGAKI,CHIN-ICHI MINAMI,TAKAAKI HAGIWARA,KAZUNORI FURUSAWA,TAKESHI FUURUNO,KEN UCHIDA,MASAAKI TERASAWA,KOUBU YAMAZAKI.
12. “A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications” April 1990number 2 vol.25 ;YOSHIHISA IWATA,MASAKI MOMODOMI,TOMOHARU TANAKA,HIDEKO OODAIRA,YASUO ITOH,RYOZO NAKAYAMA,RYOUHEI KIRISAWA,SEIICHI ARITOME,TETSUO ENDOH, RIICHIRO SHIROTA,KAZUNORI OHUCHI,FUJO MASUOKA.
13. “A 60-ns 16Mb Flash EEPROM with Program and Erase Sequence Controller” November 1991 number 11 vol.26;TAKESHI NAKAYAMA,SHIN-ICHI KOBAYASHI,YOSHIKAZU MIYAWAKI,YASUSHI TERADA,NATSUO AJIKA,MAKOTO OHI,HIDEAKI ARIMA,TAKAYUKI MATSUKAWA,TSUTOMU YOSHIHARA,KIMIO SUZUKI.
14. “A Dual-Mode Sensing Scheme of Capacitor-coupled EEPROM Cell” April 1992 number 4 vol.27; MASANORI HAYASUIKOSHI ,HIDETO HIDAKA,KAZUTAMI ARIMOTO, KAZUYASU FUJISHIMA.
15. “A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller” April 1992 number 4 vol.24; CLINTON KUO,MARK WEIDNER,THOMAS TOMS,HENRY CHOE,KO-MIN CHANG,ANN HARWOOD,JOSEPH JELEMENSKY,PHILIP SMITH.
16. “A 5-v-Only Operation0.6 mm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure” November 1998 number 11 vol.27; AKIRA UMEZAWA ,SHIGERU ATSUMI,MASAO KURIYAMA,HIRONORI BANDA,KEN-ICHI IMAMIYA,KIYOMI NARUKE,SEIJI YAMADA,ETSUSHI OBI,MASAMITSU OSHIKIRI,TOMOKO SUZUKI,SUMIO TANAKA.
17. “High-Voltage Regulation and Process Consideration for High-Density 5V-Only EEPROM’S ”October 1983 number 5 vol. sc-18; DUANE H . OTO,VINOD K. DHAM, KEITH H. GUDGER,MICHAEL J. REITSMA, GEOFFREY S. GONGWER,YAW WEN HU,JAY F. OLUND,H.STANLEY JONES,SIDNEY T. K. NIEH.
18. “A 16 kbit Smart 5V-Only EEPROM with Redundancy”. October 1983 number 5 vol.sc-18;ELROY M. LUCERO,NAGESH CHALLA ,JULIAN FIELDS,JR.
19. “A 35-ns 64K EEPROM” October 1985 number 5 vol.sc-20;CAMPBELL,DAVID L. TENNANT ,JAY F.OLUND,ROBERT B. LEFFERTS,BRENDAN T. CREMEN,PHILIP A. ANDREWS.
20. “A Temperature-and Process Tolerant 64K EEPROM .”October 1985 number 5 vol.sc-20;COLIN S.BILL,PAUL I. SUCIU, MICHAEL S. BRINER, DARRELL D. RINERSON.
21. “An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell”. October 1986 number 5 vol.sc-21; JUN-ICHI MIYAMOTO, JUN-ICHI TSUJI-MOTO,NAOHIRO MATSUKAWA,SHIGERU MORITA,KAZUYOSI SHINADA,HIROSHI NOZAWA,TETSUA IIZUKA.
22. “A Four-state EEPROM using Floating-Gate Memory Cells ”June 1987 number 3 vol.sc-22; CHRISTOPH BLEIKER, HANS MELCHIOR.77
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